uc1842/3/4/5 uc2842/3/4/5 uc3842/3/4/5 current mode pwm controller features ? optimized for off-line and dc to dc converters ? low start up current (<1ma) ? automatic feed forward compensation ? pulse-by-pulse current limiting ? enhanced load response characteristics ? under-voltage lockout with hysteresis ? double pulse suppression ? high current totem pole output ? internally trimmed bandgap reference ? 500khz operation ? low r o error amp description the uc1842/3/4/5 family of control ics provides the necessary features to implement off-line or dc to dc fixed frequency current mode control schemes with a minimal external parts count. internally implemented circuits include under-voltage lockout featuring start up current less than 1ma, a precision reference trimmed for accuracy at the error amp input, logic to insure latched operation, a pwm comparator which also provides current limit control, and a totem pole output stage designed to source or sink high peak current. the output stage, suitable for driving n channel mosfets, is low in the off state. differences between members of this family are the under-voltage lockout thresholds and maximum duty cycle ranges. the uc1842 and uc1844 have uvlo thresholds of 16v (on) and 10v (off), ideally suited to off-line applications. the corresponding thresholds for the uc1843 and uc1845 are 8.4v and 7.6v. the uc1842 and uc1843 can operate to duty cycles approaching 100%. a range of zero to 50% is obtained by the uc1844 and uc1845 by the addition of an internal toggle flip flop which blanks the output off every other clock cycle. block diagram a/b note 1: a = dil-8 pin number. b = so-14 and cfp-14 pin number. note 2: toggle flip flop used only in 1844 and 1845. slus223a - april 1997 - revised may 2002 application info available
2 uc1842/3/4/5 uc2842/3/4/5 uc3842/3/4/5 absolute maximum ratings (note 1) supply voltage (low impedance source) . . . . . . . . . . . . . . 30v supply voltage (i cc < 30ma) . . . . . . . . . . . . . . . . . self limiting output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1a output energy (capacitive load). . . . . . . . . . . . . . . . . . . . . 5 j analog inputs (pins 2, 3). . . . . . . . . . . . . . . . . . . -0.3v to +6.3v error amp output sink current . . . . . . . . . . . . . . . . . . . . 10ma power dissipation at t a 25 ( dil ?8) ..................1? power dissipation at t a 25c (soic-14) . . . . . . . . . . 725mw storage temperature range . . . . . . . . . . . . . . -65c to +150c lead temperature (soldering, 10 seconds) . . . . . . . . . . 300c note 1: all voltages are with respect to pin 5. all currents are positive into the specified terminal. consult packaging section of databook for thermal limitations and considerations of packages. connection diagrams dil-8, soic-8 (top view) n or j package, d8 package plcc-20 (top view) q package soic-14, cfp-14. (top view) d or w package package pin function function pin n/c 1 comp 2 n/c 3 n/c 4 v fb 5 n/c 6 i sense 7 n/c 8 n/c 9 r t /c t 10 n/c 11 pwr gnd 12 ground 13 n/c 14 output 15 n/c 16 v c 17 v cc 18 n/c 19 v ref 20 package ta 25c power rating derating factor above ta 25c ta 70c power rating ta 85c power rating ta 125c power rating w 700 mw 5.5 mw/c 452 mw 370 mw 150 mw dissipation rating table
3 parameter test conditions uc1842/3/4/5 uc2842/3/4/5 uc3842/3/4/5 units min typ max min typ max reference section output voltage t j = 25c, i o = 1ma 4.95 5.00 5.05 4.90 5.00 5.10 v line regulation 12 v in 25v 6 20 6 20 mv load regulation 1 i 0 20ma 6 25 6 25 mv temp. stability (note 2) (note 7) 0.2 0.4 0.2 0.4 mv/c total output variation line, load, temp. (note 2) 4.9 5.1 4.82 5.18 v output noise voltage 10hz f 10khz, t j = 25c (note2) 50 50 v long term stability t a = 125c, 1000hrs. (note 2) 5 25 5 25 mv output short circuit -30 -100 -180 -30 -100 -180 ma oscillator section initial accuracy t j = 25c (note 6) 47 52 57 47 52 57 khz voltage stability 12 v cc 25v 0.2 1 0.2 1 % temp. stability t min t a t max (note 2) 5 5 % amplitude v pin 4 peak to peak (note 2) 1.7 1.7 v error amp section input voltage v pin 1 = 2.5v 2.45 2.50 2.55 2.42 2.50 2.58 v input bias current -0.3 -1 -0.3 -2 a a vol 2 v o 4v 65 90 65 90 db unity gain bandwidth (note 2) t j = 25c 0.7 1 0.7 1 mhz psrr 12 v cc 25v 60 70 60 70 db output sink current v pin 2 = 2.7v, v pin 1 = 1.1v 2 6 2 6 ma output source current v pin 2 = 2.3v, v pin 1 = 5v -0.5 -0.8 -0.5 -0.8 ma v out high v pin 2 = 2.3v, r l = 15k to ground 5 6 5 6 v v out low v pin 2 = 2.7v, r l = 15k to pin 8 0.7 1.1 0.7 1.1 v current sense section gain (notes 3 and 4) 2.85 3 3.15 2.85 3 3.15 v/v maximum input signal v pin 1 = 5v (note 3) 0.9 1 1.1 0.9 1 1.1 v psrr 12 v cc 25v (note 3) (note 2) 70 70 db input bias current -2 -10 -2 -10 a delay to output v pin 3 = 0 to 2v (note 2) 150 300 150 300 ns uc1842/3/4/5 uc2842/3/4/5 uc3842/3/4/5 electrical characteristics: unless otherwise stated, these specifications apply for -55c t a 125c for the uc184x; -40c t a 85c for the uc284x; 0 c t a 70c for the 384x; v cc = 15v (note 5); r t = 10k; c t = 3.3nf, t a =t j. note 2: these parameters, although guaranteed, are not 100% tested in production. note 3: parameter measured at trip point of latch with v pin 2 = 0. note 4: gain defined as a vpin vpin vpin v =? ? ? 1 3 0308 ,. note 5: adjust v cc above the start threshold before setting at 15v. note 6: output frequency equals oscillator frequency for the uc1842 and uc1843. output frequency is one half oscillator frequency for the uc1844 and uc1845. note 7: temperature stability, sometimes referred to as average temperature coefficient, is described by the equation: temp stability v max vref min tj max tj min ref = ? ? () () () () v ref (max) and v ref (min) are the maximum and minimum reference voltages measured over the appropriate temperature range. note that the extremes in voltage do not necessarily occur at the extremes in temperature.
4 parameter test condition uc1842/3/4/5 uc2842/3/4/5 uc3842/3/4/5 units min typ max min typ max output section output low level i sink = 20ma 0.1 0.4 0.1 0.4 v i sink = 200ma 1.5 2.2 1.5 2.2 v output high level i source = 20ma 13 13.5 13 13.5 v i source = 200ma 12 13.5 12 13.5 v rise time t j = 25c, c l = 1nf (note 2) 50 150 50 150 ns fall time t j = 25c, c l = 1nf (note 2) 50 150 50 150 ns under-voltage lockout section start threshold x842/4 15 16 17 14.5 16 17.5 v x843/5 7.8 8.4 9.0 7.8 8.4 9.0 v min. operating voltage after turn on x842/4 9 10 11 8.5 10 11.5 v x843/5 7.0 7.6 8.2 7.0 7.6 8.2 v pwm section maximum duty cycle x842/3 95 97 100 95 97 100 % x844/5 46 48 50 47 48 50 % minimum duty cycle 0 0 % total standby current start-up current 0.5 1 0.5 1 ma operating supply current v pin 2 =v pin 3 = 0v 11 17 11 17 ma v cc zener voltage i cc = 25ma 30 34 30 34 v note 2: these parameters, although guaranteed, are not 100% tested in production. note 3: parameter measured at trip point of latch with v pin 2 = 0 . note 4: gain defined as: a vpin vpin vpin v =? ? ? 1 3 0308 ;. . note 5: adjust v cc above the start threshold before setting at 15v. note 6: output frequency equals oscillator frequency for the uc1842 and uc1843. output frequency is one half oscillator frequency for the uc1844 and uc1845. uc1842/3/4/5 uc2842/3/4/5 uc3842/3/4/5 electrical characteristics: unless otherwise stated, these specifications apply for ? 55c t a 125c for the uc184x; ? 40c t a 85c for the uc284x; 0 c t a 70c for the 384x; v cc = 15v (note 5); r t = 10k; c t = 3.3nf, t a =t j. error amp configuration error amp can source or sink up to 0.5ma
5 uc1842/3/4/5 uc2842/3/4/5 uc3842/3/4/5 under-voltage lockout current sense circuit oscillator section during under-voltage lock-out, the output driver is biased to sink minor amounts of current. pin 6 should be shunted to ground with a bleeder resistor to prevent activating the power switch with extraneous leakage currents. a small rc filter may be required to suppress switch transients . peak current (i s ) is determined by the formula i smax rs
6 high peak currents associated with capacitive loads ne - cessitate careful grounding techniques. timing and by - pass capacitors should be connected close to pin 5 in a single point ground. the transistor and 5k potentiometer are used to sample the oscillator waveform and apply an adjustable ramp to pin 3. shutdown of the uc1842 can be accomplished by two methods; either raise pin 3 above 1v or pull pin 1 below a voltage two diode drops above ground. either method causes the output of the pwm comparator to be high (refer to block diagram). the pwm latch is reset domi - nant so that the output will remain low until the next clock cycle after the shutdown condition at pin 1 and/or 3 is removed. in one example, an externally latched shutdown may be accomplished by adding an scr which will be reset by cycling v cc below the lower uvlo threshold. at this point the reference turns off, al - lowing the scr to reset. uc1842/3/4/5 uc2842/3/4/5 output saturation characteristics error amplifier open-loop frequency response open-loop laboratory fixture shut down techniques
7 uc1842/3/4/5 uc2842/3/4/5 uc3842/3/4/5 offline flyback regulator slope compensation a fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope compensation for converters requiring duty cycles over 50%. power supply specifications 1. input voltages 5vac to 130va (50 hz/60hz) 2. line isolation 3750v 3. switching frequency 40khz 4. efficiency at full load 70% 5. output voltage: a. +5v, 5%; 1a to 4a load ripple voltage: 50mv p-p max b. +12v, 3%; 0.1a to 0.3a load ripple voltage: 100mv p-p max c. -12v , 3%; 0.1a to 0.3a load ripple voltage: 100mv p-p max
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